pub fn logical_signature(
sim: &Simulator,
outputs: &[(&OutputLogical, (bool, bool))],
) -> Result<Vec<f64>, ExecError>Expand description
Compute all nonidentity joint Pauli expectations of the live logical outputs.
Values are corrected by their (X, Z) frame bits. Output zero is the
least-significant base-four digit, with digits I, X, Y, Z. This determines
the full reduced logical state, including entanglement, without measuring it.
Representatives of different widths are extended with trailing identities.
For n outputs, this allocates 4^n - 1 values and makes that many exact
simulator expectation reads; use it only for small output registers.
ยงErrors
ExecError::LogicalSignatureTooLarge if 4^n overflows usize;
otherwise propagates engine errors from malformed logical observables.